1. Field of the Invention
Embodiments of the invention relate to methods for fabricating a semiconductor device. In particular, embodiments of the invention relate to methods for fabricating a semiconductor device comprising at least one of a complementary metal oxide semiconductor (CMOS) transistor and a silicon-on-insulator substrate.
This application claims priority to Korean Patent Application No. 2006-0030095, filed on Apr. 3, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
In general, a CMOS transistor has a structure comprising an N-channel metal oxide semiconductor (NMOS) transistor and a P-channel metal oxide semiconductor (PMOS) transistor. When a channel region of the NMOS transistor includes single-crystalline silicon, the NMOS transistor will have relatively good electrical performance. In addition, when a channel region of the PMOS transistor includes single-crystalline silicon-germanium, the PMOS transistor will have relatively good electrical performance.
Accordingly, there has been recent, active investigation into technology for fabricating a semiconductor device comprising an NMOS transistor and a PMOS transistor, wherein the NMOS transistor comprises a channel region including single-crystalline silicon and the PMOS transistor comprises a channel region including single-crystalline silicon-germanium. In addition, as the demand for finer patterns within the semiconductor device increases, the width of an isolation layer separating a region having the NMOS transistor from a region having the PMOS transistor is required to be less than about 50 nm.
However, using a conventional method, it is difficult to fabricate a semiconductor device that includes an isolation layer having a width of less than about 50 nm and also includes a channel region including single-crystalline silicon and another channel region including single-crystalline silicon-germanium.